Enhancing Error Detection Performance through Parallel CRC Computation on Multi-Core Architectures

Document Type : Research Article

Authors

Computer Engineering and Information Technology Department, Razi University, Kermanshah, Iran.

10.22108/jcs.2026.148544.1198

Abstract

Cyclic Redundancy Check (CRC) remains one of the most widely used error-detection mechanisms in communication, storage, and embedded systems. However, conventional software CRC implementations suffer from inherent sequential dependencies that limit efficient utilization of modern multi-core processors. This paper presents a generalized software-based parallel CRC framework for multi-core architectures using POSIX threads (pthreads). The proposed framework supports multiple CRC variants, including CRC-8, CRC-16, CRC-32, CRC-64, and CRC-128, within a unified implementation model. {To preserve correctness during parallel execution, the framework employs a GF(2)-based CRC combination mechanism rather than naïve XOR aggregation. The combine stage is formulated using polynomial arithmetic and matrix-based shifting operations over GF(2), ensuring equivalence between parallel and serial CRC computation. The proposed method was evaluated using multiple workload sizes and thread configurations. Experimental analysis includes execution time, throughput, latency, scalability behavior, and energy estimation under varying thread counts. Results indicate that parallel execution significantly improves performance for large datasets, achieving approximately 3--4x speedup on the evaluated platform while preserving exact CRC correctness. Comparative discussion with representative CRC optimization approaches, including lookup-table methods, slicing-by-8, SIMD/vectorized CRC, and hardware-assisted CRC techniques, is also provided to position the proposed framework within the broader CRC optimization landscape. Although the presented framework emphasizes portability, multi-variant support, and correctness-preserving software parallelization, scalability remains influenced by synchronization overhead, memory bandwidth constraints, and hardware characteristics. Overall, the proposed approach provides a portable and generalized software framework for correctness-preserving parallel CRC acceleration on general-purpose multi-core systems.

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References

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History

  • Receive Date: 27 February 2026
  • Revise Date: 02 July 2026
  • Accept Date: 27 July 2026

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