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    <title>Journal of Computing and Security</title>
    <link>https://jcomsec.ui.ac.ir/</link>
    <description>Journal of Computing and Security</description>
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    <pubDate>Wed, 01 Jul 2026 00:00:00 +0330</pubDate>
    <lastBuildDate>Wed, 01 Jul 2026 00:00:00 +0330</lastBuildDate>
    <item>
      <title>Centrality Analysis of a Weighted Iranian Provinces Adjacency Network</title>
      <link>https://jcomsec.ui.ac.ir/article_30573.html</link>
      <description>Recently, network theory has gained prominence for modeling and analyzing a wide range of phenomena to achieve a deeper understanding. In this paper, an undirected weighted network is employed to model the adjacency structure of the provinces of Iran. Each province is represented by a node in the network, and whenever two provinces share a boundary, a weighted edge is established between them. The edge weight is determined by the distance between the centers of the two adjacent provinces and lies in the interval [0,1]; closer provincial centers yield weights nearer to 1. The resulting network, hereafter termed the Weighted Iranian Provinces Adjacency Network (WIPAN), is analyzed to extract key network statistics. However, the core focus of the study involves the computation of various centrality measures on this network. For this analysis, twelve well-established centrality metrics-widely utilized in network science literature-were selected. This suite encompasses both fundamental measures, such as degree, closeness, and betweenness centrality, and more advanced or hybrid methods, including Katz, eigenvector, PageRank, and Laplacian centrality. Each method, viewed from its own standpoint, answers which nodes are most central in the network. Based on a consensus ranking of the centrality measures, node 10 emerges as the most central node in the network, while node 22 is the least central. The findings of this study establish a foundational basis for further analyses and can be applied to a broad range of planning problems as well as to decision-making at both micro and macro levels.</description>
    </item>
    <item>
      <title>Model-Driven Framework for Automatic Generation of Auction-Based Coordination Strategies for Crisis Response</title>
      <link>https://jcomsec.ui.ac.ir/article_30378.html</link>
      <description>Coordination strategies for crisis response mainly deal with task allocation. Auction-based coordination strategies are one of the most common strategies for task allocation in Emergency Response Environments (ERE), i.e., the environments in which the crisis occurs. Due to the emergency in EREs, coordination must be performed efficiently. To this end, before a crisis occurs, crisis managers try to benefit from modeling and simulation of coordination strategies. However, programming for the simulation of different coordination strategies is a difficult and time-consuming task for domain experts who usually do not have enough programming skills. To overcome this issue, in this paper, we propose a model-driven framework for modeling and automatic generation of auction-based coordination strategies for crisis response. The proposed framework consists of two main parts: (1) a Domain-Specific Modeling Language (DSML), named Auction-ML, with tool support for designing auction-based coordination strategies at a high level of abstraction, and (2) a transformation engine for automatic code generation from designed models. The generated code can be executed on ERE models to &amp;amp;lrm;generate the output model that shows &amp;amp;lrm;team formations, &amp;amp;lrm;task allocations, resource &amp;amp;lrm;allocation, and &amp;amp;lrm;strategy performance. To show the applicability of the proposed framework, two inter- and intra-organizational auction-based coordination strategies are modeled using AuctionML. &amp;amp;lrm;Then, the performance of the strategies is measured &amp;amp;lrm;by the automatic &amp;amp;lrm;generation of coordination strategies and&amp;amp;lrm; execution &amp;amp;lrm;of the &amp;amp;lrm;strategies on the ERE models.&amp;amp;lrm; The results confirm the applicability of the framework for enabling non-programmers to model, simulate, and evaluate auction-based strategies.</description>
    </item>
    <item>
      <title>Enhancing Error Detection Performance through Parallel CRC Computation on Multi-Core Architectures</title>
      <link>https://jcomsec.ui.ac.ir/article_30666.html</link>
      <description>Cyclic Redundancy Check (CRC) remains one of the most widely used error-detection mechanisms in communication, storage, and embedded systems. However, conventional software CRC implementations suffer from inherent sequential dependencies that limit efficient utilization of modern multi-core processors. This paper presents a generalized software-based parallel CRC framework for multi-core architectures using POSIX threads (pthreads). The proposed framework supports multiple CRC variants, including CRC-8, CRC-16, CRC-32, CRC-64, and CRC-128, within a unified implementation model. {To preserve correctness during parallel execution, the framework employs a GF(2)-based CRC combination mechanism rather than na&amp;amp;iuml;ve XOR aggregation. The combine stage is formulated using polynomial arithmetic and matrix-based shifting operations over GF(2), ensuring equivalence between parallel and serial CRC computation. The proposed method was evaluated using multiple workload sizes and thread configurations. Experimental analysis includes execution time, throughput, latency, scalability behavior, and energy estimation under varying thread counts. Results indicate that parallel execution significantly improves performance for large datasets, achieving approximately 3--4x speedup on the evaluated platform while preserving exact CRC correctness. Comparative discussion with representative CRC optimization approaches, including lookup-table methods, slicing-by-8, SIMD/vectorized CRC, and hardware-assisted CRC techniques, is also provided to position the proposed framework within the broader CRC optimization landscape. Although the presented framework emphasizes portability, multi-variant support, and correctness-preserving software parallelization, scalability remains influenced by synchronization overhead, memory bandwidth constraints, and hardware characteristics. Overall, the proposed approach provides a portable and generalized software framework for correctness-preserving parallel CRC acceleration on general-purpose multi-core systems.</description>
    </item>
    <item>
      <title>Enhancing Low-Resolution Persian License Plates via Diffusion Models</title>
      <link>https://jcomsec.ui.ac.ir/article_30687.html</link>
      <description>With the rapid growth of urbanization and the increasing number of vehicles, automatic license plate recognition systems have become an essential component of traffic monitoring and management. However, the accuracy of these systems decreases when the captured plate images have low resolution or are affected by environmental noise. This study investigates the use of diffusion models to enhance the resolution of Iranian license plate images under such challenging conditions. In the proposed framework, a diffusion-based denoising process progressively reconstructs and refines image details iteratively. Experimental evaluations demonstrate that the proposed method outperforms well-known approaches such as Bicubic interpolation and deep learning-based super-resolution models, including SRGAN, Real-ESRGAN, BSRGAN, and SwinIR, in terms of perceptual quality and objective metrics. Specifically, the model achieves a PSNR of 31.2458 and an SSIM of 0.8621. Moreover, OCR results indicate that the reconstructed images produced by the diffusion model lead to better character readability and enhanced recognition accuracy.</description>
    </item>
    <item>
      <title>Boomeyong Cryptanalysis of Reduced-Round mCrypton</title>
      <link>https://jcomsec.ui.ac.ir/article_30616.html</link>
      <description>Given the growing demand for secure yet lightweight encryption in constrained environments such as RFID tags and wireless sensor networks, resource-constrained devices are increasingly relying on lightweight block ciphers to protect sensitive data while meeting strict power, area, and latency requirements. In response to the challenge of designing such block ciphers, several lightweight block ciphers, such as the mCrypton, have been proposed. However, a thorough security evaluation of such ciphers is crucial, since their vulnerabilities can threaten the entire security architecture of systems. In this paper, we present the first application of the boomeyong attack&amp;amp;mdash;a hybrid technique combining boomerang and yoyo frameworks&amp;amp;mdash;on the reduced-round mCrypton block cipher. We formulate a novel 5-round distinguisher and demonstrate a key recovery attack that improves upon all previously known results. By refining structural definitions and adapting the boomeyong framework to the SPN-based design of mCrypton, our attack achieves a data complexity of 226, a time complexity of 223.02En. +225XOR, and a memory complexity of 212&amp;amp;nbsp;blocks.</description>
    </item>
    <item>
      <title>Design of Memristive Lightweight Encryption For In-Memory Image Steganography</title>
      <link>https://jcomsec.ui.ac.ir/article_30916.html</link>
      <description>With the expansion of data-intensive applications and increasing data volumes, providing an efficient solution to address growing energy consumption and performance degradation caused by the transfer of large amounts of data between the processor and the main memory has become a severe challenge. The frequent transfer of large amounts of data between internal chip units, memories, and their interconnections exacerbates the vulnerability of the data being accessed. Employing a memristive Computation In-Memory-Array (CIM-A) architecture limits data transfer, thereby addressing both challenges. By integrating lightweight cryptography, developed to be applied in hardware-constrained devices, with CIM-A architectures, the significant energy and latency overheads associated with a high rate of data transfers across the architecture’s main blocks and interconnections can be mitigated. This paper implements two standard lightweight stream ciphers, Trivium and Grain-128a, for CIM using stateful material implication (IMPLY) logic to address the performance challenges. In addition to redesigning the cryptographic structures, we reduce the hardware complexity of conventional IMPLY-based implementations by proposing an efficient method for shifting data within the shift registers. Applying the proposed data-shifting method to the registers of these ciphers reduces the number of computational steps and decreases memristors&amp;amp;#039; energy consumption by up to 42% and 44%, respectively, compared to conventional implementations. Finally, the performance of the proposed circuits is evaluated in a steganography application, demonstrating their practical efficiency.</description>
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