A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set

Authors

1 Faculty of Computer Science and Engineering, Shahid Beheshti University, GC, Tehran, Iran

2 Faculty of Marine Engineering, Khorramshahr University of Marine Science and Technology, Khuzestan, Iran

3 Electronic Engineering Department, Islamic Azad University, Central Tehran Branch, Tehran, Iran

Abstract

The moduli set 2 n−1 − 1, 2 n+1 − 1, 2 n , 2 n − 1 has been recently proposed inliterature for class of 4n-bit dynamic range in residue number system. Due toonly utilizing modulus in the form of 2 k − 1 besides modulo 2 n , this moduliset enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only doesthe efficiency of a RNS system depend on the residue arithmetic unit but italso is limited to the residue to binary converter. In this paper, a new two levelresidue-to-binary converter architecture based on Mixed Radix Conversion(MRC) is presented for the aforementioned moduli set. The proposed converterincludes two levels of design based on MRC properties. Firstly, the 3-modulisubset 2 n−1 − 1, 2 n+1 − 1, 2 n − 1 is properly organized and as it does notcalculate several values, it results in some cost modifications. Eventually, atwo-moduli set 2 n−1 − 1 2 n+1 − 1 (2 n − 1) , 2 n is formed to compute thebinary of RNS counterpart. The proposed architecture is shown to be moreefficient both in terms of hardware cost and conversion delay in comparisonwith the related state-of-the-art works.

Keywords

Journal of Computing and Security
Volume 2, Issue 1 - Serial Number 1
5
January 2015
Pages 43-54

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History

  • Receive Date: 06 January 2014
  • Revise Date: 26 May 2018
  • Accept Date: 25 September 2017

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