%0 Journal Article
%T A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set
%J Journal of Computing and Security
%I University of Isfahan & Iranian Society of Cryptology
%Z 2322-4460
%A Taheri, MohammadReza
%A Shafiee, Nasim
%A Esmaeildoust, Mohammad
%A Amirjamshidi, Zhale
%A Sabbaghi-nadooshan, Reza
%A Navi, Keivan
%D 2015
%\ 01/01/2015
%V 2
%N 1
%P 43-54
%! A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set
%K Mixed Radix Conversion
%K Residue Arithmetic
%K Residue Number System
%K Residue-to-Binary Converter
%R
%X The moduli set 2 n−1 − 1, 2 n+1 − 1, 2 n , 2 n − 1 has been recently proposed inliterature for class of 4n-bit dynamic range in residue number system. Due toonly utilizing modulus in the form of 2 k − 1 besides modulo 2 n , this moduliset enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only doesthe efficiency of a RNS system depend on the residue arithmetic unit but italso is limited to the residue to binary converter. In this paper, a new two levelresidue-to-binary converter architecture based on Mixed Radix Conversion(MRC) is presented for the aforementioned moduli set. The proposed converterincludes two levels of design based on MRC properties. Firstly, the 3-modulisubset 2 n−1 − 1, 2 n+1 − 1, 2 n − 1 is properly organized and as it does notcalculate several values, it results in some cost modifications. Eventually, atwo-moduli set 2 n−1 − 1 2 n+1 − 1 (2 n − 1) , 2 n is formed to compute thebinary of RNS counterpart. The proposed architecture is shown to be moreefficient both in terms of hardware cost and conversion delay in comparisonwith the related state-of-the-art works.
%U https://jcomsec.ui.ac.ir/article_21874_ae1328488436df6666e684861e83e600.pdf